TSMC is preparing everything so that the surface of the chips (CPUGPU, SoC, etc.) will be larger in the future with their technology CoWoS.
TSMC wants bigger CPUs and GPUs with CoWoS technology
CoWoS It is a packaging technology that already exists today and that TSMC implemented in chip manufacturing. However, they are announcing that in the future there will be an update to this technology that will offer a larger chip surface, which will allow for more transistors.
There is a physical limitation of the chips currently manufactured that they cannot exceed a surface area of ​​around 800 mm2. If you want to build large processors or GPUs, you have to use chiplets and interconnect them so that they work together. What you propose TSMC with its technology CoWoS (Chip-on-Wafer-on-Substrate) is to increase this size. CoWoS already allows chips up to 2800 mm2, but this will not be enough.
These size limits are already being reached with the new accelerators AMD Instinct MI300 or the B200 from Nvidia, so in the future it will be necessary to eliminate the physical limitations of chip lithography and be able to manufacture them in a larger size.
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On a slide, TSMC anticipates that chips about 5.5 times larger than the current reticle could be createdwhich will allow increasing computational performance by 3.5 times compared to the current chips created with CoWoS by the year 2026, by the year 2027 chips with up to 7 times the computational performance can be created with 8 times the reticle limit.
By 2027, chip sizes could be up to 120 x 120 mm. Of course, we are always talking about an implementation in the segment of data centers, servers, etc. Chips of this size in PCs or laptops would not be viable in terms of physical space, electrical consumption and heat generation, at least in the short term. We will keep you informed.
